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Role of Device Dimensions and Layout on the Analog Performance of Gate-First HKMG nMOS Transistors

DSpace at IIT Bombay

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Title Role of Device Dimensions and Layout on the Analog Performance of Gate-First HKMG nMOS Transistors
 
Creator SIVANARESH, MS
DUHAN, P
MOHAPATRA, NR
 
Subject NITROGEN INCORPORATION
HAFNIUM OXIDE
IMPLANTATION
MOSFETS
High-K dielectric
high-K gate dielectrics and metal gate (HKMG)
intrinsic gain
layout-dependent effects
metal gate
MOS transistor
narrow-width effect
oxygen vacancies
threshold voltage
transconductance
transconductance generation efficiency
 
Description This paper discusses in detail the effects of device dimensions and layout/design rules on the analog performance of gate-first high-K gate dielectrics and metal gate (HKMG) nMOS transistors. It is observed through detailed measurements that the transconductance of HKMG nMOS transistors increases with the reduction in the channel width. The 80-nm wide HKMG nMOS transistors show 1.3x improvement in the intrinsic gain and similar to 27% improvement in the transconductance generation efficiency compared with a 1000-nm wide transistor. The similar behavior is observed for all gate lengths. The physical mechanisms responsible for this behavior are identified and explained. It is finally shown that the analog performance of the HKMG nMOS transistors could be further improved by dividing a single active finger into multiple active fingers, by increasing active-to-active spacing, by increasing the gate pitch, and by eliminating the active dummies.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2016-01-15T09:11:37Z
2016-01-15T09:11:37Z
2015
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(11)3792-3798
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2015.2477368
http://dspace.library.iitb.ac.in/jspui/handle/100/18243
 
Language en