Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models
Electronic Theses of Indian Institute of Science
View Archive InfoField | Value | |
Title |
Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models
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Creator |
Balssubramanian, Suresh
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Subject |
Computer Aided Design
Integrated Circuits Phased Locked Loop Phased Locked Loop Design - Behavioral Models PLL Design Digital Signal Processing (DSP) Application Specific Integrated Circuits (ASIC) Phase Frequency Detector (PFD) Voltage Controlled Oscillators (VCO) Electronic Engineering |
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Contributor |
Jamadagni, H S
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Date |
2011-04-13T03:59:32Z
2011-04-13T03:59:32Z 2011-04-13 2004-04 |
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Type |
Thesis
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Identifier |
http://hdl.handle.net/2005/1127
http://etd.ncsi.iisc.ernet.in/abstracts/1477/G19577-Abs.pdf |
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Language |
en_US
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Relation |
G19577
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