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Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

Electronic Theses of Indian Institute of Science

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Field Value
 
Title Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
 
Creator Valluri, Madhavi Gopal
 
Subject Compiling (Electronic Computers)
Multiprocessors
Instruction Scheduling
Compilers
Register Allocation
Machine Models
Instruction-Level Parallelism (ILP)
Very Long Instruction Word (VLIW) Processors
Modulo-Variable Expansion (MVE)
Sensitive Scheduling
Computer Science
 
Contributor Govindarajan, R
 
Date 2011-11-16T05:13:48Z
2011-11-16T05:13:48Z
2011-11-16
1999-01
 
Type Thesis
 
Identifier http://etd.iisc.ernet.in/handle/2005/1532
http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdf
 
Language en_US
 
Relation G23229