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Modal based analysis of binary adders with fault tolerance using QCA in marine applications

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Title Modal based analysis of binary adders with fault tolerance using QCA in marine applications
 
Creator Banu, K.Sabitha
Karuppasamy, P.
Selvaperumal, S.
Pugazhenthi, P. Nedumal
 
Subject Area-Delay Product
Cell minimization techniques
Binary adders
Quantum-dot cellular Automata
 
Description 1069-1075
This paper explains an efficient design and analysis of binary adders using Quantum-dot cellular Automata (QCA) tools. Main goal of this work such as faster speed, smaller size, and less area than transistor based technology. The 64 bit binary adders are modeled using cell minimization techniques and detailed simulation using QCAD. Techniques are used two cells inverter and suitable arrangement of cells without overlapping of neighboring cells. These structures are designed with minimum number of cells in adders by using cell minimization techniques . Performance of 64 bit adder results the less area, delay and achieved the minimum area delay product (ADP).
 
Date 2017-05-08T07:58:49Z
2017-05-08T07:58:49Z
2017-05
 
Type Article
 
Identifier 0975-1033 (Online); 0379-5136 (Print)
http://nopr.niscair.res.in/handle/123456789/41645
 
Language en_US
 
Rights CC Attribution-Noncommercial-No Derivative Works 2.5 India
 
Publisher NISCAIR-CSIR, India
 
Source IJMS Vol.46(05) [May 2017]