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Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell

Electronic Theses of Indian Institute of Science

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Title Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell
 
Creator Sarkar, Manju
 
Subject Electrical Communications
Random access storage
MOSFET
Static Random Access Memory
Iambda Bipolar Transistor (LBT)
DC model
Sram Cell
 
Description With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the
possibility of fabrication of LBTs with a CMOS technology is established.

Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same.

A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
 
Publisher Indian Institute of Science
 
Contributor Satyam, M
Prabhakar, A
 
Date 2005-07-07T09:01:04Z
2005-07-07T09:01:04Z
2005-07-07T09:01:04Z
1995-06
 
Type Electronic Thesis and Dissertation
 
Format 4164618 bytes
application/pdf
 
Identifier http://etd.iisc.ernet.in/handle/2005/124
null
 
Language en
 
Rights I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.