Compiler Techniques For Code Size And Power Reduction For Embedded Processors
Electronic Theses of Indian Institute of Science
View Archive InfoField | Value | |
Title |
Compiler Techniques For Code Size And Power Reduction For Embedded Processors
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Creator |
Sarvani, V V N S
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Subject |
Microprocessors
Embedded Systems Compilers Embedded Processors Computer Science |
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Contributor |
Govindarajan, R
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Date |
2011-04-28T09:32:58Z
2011-04-28T09:32:58Z 2011-04-28 2004-06 |
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Type |
Thesis
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Identifier |
http://etd.iisc.ernet.in/handle/2005/1135
http://etd.ncsi.iisc.ernet.in/abstracts/1489/G18678-Abs.pdf |
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Language |
en_US
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Relation |
G18678
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