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Design and analysis of an efficient architecture of logarithmic multiplier and its applications

Shodhganga@INFLIBNET

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Title Design and analysis of an efficient architecture of logarithmic multiplier and its applications
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Contributor Kanungo,Jitendra and Mahajan, Anurag
 
Subject Algorithm For Logarithmic
Architecture of Logarithmic
Gaussian Smoothing Filter
Improved Operand Decomposition
 
Description Digital signal processing applications require an efficient errorless and low power arithmetic operation Binary number arithmetic units are compromised on speed complexity Logarithm Number System addresses to these issues and overcome gaps LNS multipliers are advantageous over the Fixed Point multipliers and the Floating Point multipliers in terms of speed and accuracy
newlineLNS multiplier has two subcategories
newlinea Lookup Tables and Interpolations based multipliers
newline b Mitchell s algorithm based multipliers Mitchell s algorithm based logarithm multiplication is further subdivided into four sub-categories As Divided Approximation Correction term based Operand decomposition and MA based iterative algorithm During 2010 to 2013 works on the iterative logarithmic approximation have been proposed It was based on the correction terms with the high level of parallelism with fewer logic resources and higher speed The ASIC implementation of floating point logarithmic number system has also been reported
newlineThe computation of arithmetic based on LNS involves three steps Conversion of binary numbers in logarithmic numbers then respective arithmetic operation is performed on logarithmic numbers and then antilogarithmic conversion Many methods regarding logarithmic conversion to binary system and antilogarithmic converter have been presented in recent years Design of Leading-One Detector is important as it is used as a key component for performing shifting and normalization process in the floating point multiplication floating point addition and in binary logarithmic converters Reported LOD designs were either slower or hardware inefficient
newlineThe objective of the proposed thesis work is to explore the errorless and low power designs for the implementation of logarithm multiplication and their subcomponents such as logarithm converter and antilogarithm converter An efficient architecture of LOD is also proposed and used in a logarithm multiplier
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List of Publication
 
Date 2018-10-16T10:09:25Z
2018-10-16T10:09:25Z
21/07/2014
03/10/2018
08/10/2018
 
Type Ph.D.
 
Identifier http://hdl.handle.net/10603/218727
 
Language English
 
Relation 114
 
Rights university
 
Format xii,116p.
29.5X20.5"
None
 
Coverage Electronic and Communication Engineering
 
Publisher Guna
Jaypee University of Engineering and Technology, Guna
Department of Electronics and Communication
 
Source University