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<strong>Performance Analysis of a High-Speed High-Precision Dynamic Comparator</strong>

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Title Statement <strong>Performance Analysis of a High-Speed High-Precision Dynamic Comparator</strong>
 
Added Entry - Uncontrolled Name Dhandapani, Vaithiyanathan ; Assistant Professor Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
Mishra, Ashish ; Research Scholar Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
Kumar, Ankit ; PG Student Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
Mishra, Alok Kumar ; Research Scholar Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
Singh, Sachin ; Assistant Professor Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
Kaur, Baljit ; Assistant Professor Department of Electronics and Communication Engineering National Institute of Technology Delhi, Delhi - 110040
 
Uncontrolled Index Term Specific instrumentation and techniques of general use in physics; Elementary particles and fields
Dynamic comparator, Preamplifier, low-power analog design, high speed, low-offset, analog-to-digital-converters (ADCs)
 
Summary, etc. Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.
 
Publication, Distribution, Etc. Indian Journal of Pure & Applied Physics (IJPAP)
2022-03-16 14:31:18
 
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http://op.niscair.res.in/index.php/IJPAP/article/view/56042
 
Data Source Entry Indian Journal of Pure & Applied Physics (IJPAP); ##issue.vol## 60, ##issue.no## 3 (2022): Indian Journal of Pure & Applied Physics
 
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