Performance Analysis of a High-Speed High-Precision Dynamic Comparator
NOPR - NISCAIR Online Periodicals Repository
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Title |
Performance Analysis of a High-Speed High-Precision Dynamic Comparator
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Creator |
Dhandapani, Vaithiyanathan
Mishra, Ashish Kumar, Ankit Mishra, Alok Kumar Singh, Sachin Kaur, Baljit |
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Subject |
Dynamic comparator
Preamplifier low-power analog design high speed low-offset analog-to-digital-converters (ADCs) |
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Description |
238-245
Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit. |
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Date |
2022-04-07T11:15:58Z
2022-04-07T11:15:58Z 2022-03 |
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Type |
Article
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Identifier |
0975-0959 (Online); 0301-1208 (Print)
http://nopr.niscair.res.in/handle/123456789/59494 |
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Language |
en
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Publisher |
NIScPR-CSIR, India
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Source |
IJPAP Vol.60(03) [March 2022]
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