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Performance Analysis of a High-Speed High-Precision Dynamic Comparator

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Title Performance Analysis of a High-Speed High-Precision Dynamic Comparator
 
Creator Dhandapani, Vaithiyanathan
Mishra, Ashish
Kumar, Ankit
Mishra, Alok Kumar
Singh, Sachin
Kaur, Baljit
 
Subject Dynamic comparator
Preamplifier
low-power analog design
high speed
low-offset
analog-to-digital-converters (ADCs)
 
Description 238-245
Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.
 
Date 2022-04-07T11:15:58Z
2022-04-07T11:15:58Z
2022-03
 
Type Article
 
Identifier 0975-0959 (Online); 0301-1208 (Print)
http://nopr.niscair.res.in/handle/123456789/59494
 
Language en
 
Publisher NIScPR-CSIR, India
 
Source IJPAP Vol.60(03) [March 2022]