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A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

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Title A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology
 
Creator Mushtaq, Umayia
Akram, Md. Waseem
Prasad, Dinesh
Nagar, Bal Chand
 
Subject ASAP7 PDK
LCNT
FinFET
Schmitt Trigger
PVT
 
Description 387-394
Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power
dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects.
FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper
short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor)
technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and
comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based
Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and
35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach
at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET
Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.
 
Date 2022-05-13T09:21:42Z
2022-05-13T09:21:45Z
2022-05-13T09:21:42Z
2022-05-13T09:21:45Z
2022-05
 
Type Article
 
Identifier 0975-0959 (Online); 0301-1208 (Print)
http://nopr.niscair.res.in/handle/123456789/59713
 
Language en
 
Publisher CSIR-NIScPR, India
 
Source IJPAP Vol.60(05) [May 2022]