ICAR Research Data Repository for Knowledge Management
DSpace at IIT Bombay
View Archive InfoMetadata
| Field | Value |
| Title | VLSI implementation of artificial neural network based digital multiplier and adder |
| Names |
RANADE, RANJEET
BHANDARI, SANJAY CHANDORKAR, AN |
| Date Issued | 1996 (iso8601) |
| Abstract | This paper describes a technique to realize a novel digital multiplier using Artificial Neural Network (ANN). It proposes a generalized `Energy Function' for multiplier and its hardware realization by combining conventional digital hardware with a neural network. The design of neurons, extended range active loads and the digital multiplier are described in this paper along with the simulation results . |
| Genre | Article |
| Topic | Cmos Digital Integrated Circuit |
| Identifier | Proceedings of the Ninth International Conference on VLSI Design, Bangalore, India, 3-6 January 1996, 318-319 |