Record Details


Field	Value

Title	A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function

Names	ROY, SUBIR NARAYANAN, H
Date Issued	1991 (iso8601)
Abstract	An area efficient 2 level implementation of combinational logic can be achieved by partitioning the original PLA into several PLAs each of which interacts with the others weakly. A PLA implementing a sum of products logic functions can be modelled through a bipartite graph B G, which specifies the intersection of rows (minterms) with columns of the AND plane (primary inputs) and the OR plane (primary outputs) respectively. The authors show how to achieve a good PLA partition by using the principal lattice of partitions of the incidence function of BG
Genre	Article
Topic	Vlsi
Identifier	Proceedings of the Fourth Annual IEEE International ASIC Conference and Exhibit, Rochester, New York, 23-27 September 1991, York, P2 - 4.1-P2 - 4.4.

ICAR Research Data Repository for Knowledge Management