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| Field | Value |
| Title | Interface design for rationally clocked GALS systems |
| Names |
MEKIE, JOYCEE
CHAKRABORTY, SUPRATIK VENKATARAMANI, G THIAGARAJAN, PS SHARMA, DK |
| Date Issued | 2006 (iso8601) |
| Abstract | We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delay-augmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique. |
| Genre | Article |
| Topic | Asynchronous Circuit |
| Identifier | Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, Grenoble, France, 13-15 March 2006, 1-12 |