Record Details


Field	Value

Title	Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories

Names	SABLE, RS SARAF, RP PAREKHJI, RA CHANDORKAR, AN
Date Issued	2004 (iso8601)
Abstract	Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coupling conditions. Built-in self-test (BIST) solutions for testing memories today incorporate hardware for test pattern generation and application for a variety of these algorithms. This paper presents a BIST implementation for detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories (RAMs). These faults are of different classes and types. More specifically, active, passive and static faults for distance 1 and 2 neighbourhoods, of types 1 and 2, are considered. It is shown how the proposed address generation and test pattern generation schemes can be made scaleable for the given fault type under consideration.
Genre	Article
Topic	Automatic Test Pattern Generation
Identifier	Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, 5-9 January 2004, 753-756

ICAR Research Data Repository for Knowledge Management