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| Field | Value |
| Title | Variance reduction in Monte Carlo capacitance extraction |
| Names |
BATTERYWALA, SH
DESAI, MP |
| Date Issued | 2005 (iso8601) |
| Abstract | In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics. |
| Genre | Article |
| Topic | Monte Carlo Methods |
| Identifier | Proceedings of the 18th International Conference on VLSI Design, Kolkata, India, 3-7 January 2005, 85-90 |