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Title Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation : understanding the anomalous breakdown and optimization of P/E conditions
 
Names SINGH, P
SANDHYA, C
AULUCK, K
BISHT, G
SIVATHEJA, M
HOFMANN, R
MUKHOPADHYAY, G
MAHAPATRA, S
SINGH, PK
BISHT, KAG
SIVATHEJA, M
MUKHOPADHYAY, G
MAHAPATRA, S
HOFMANN, R
Date Issued 2010 (iso8601)
Abstract Large memory window (6-9V) program/erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant voltage stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence, and energy on the defect generation process in the gate stack. Degradation during P and E are isolated to allow individual optimization for improving the cycling reliability. P/E cycling endurance >10(4) at 8V MW and >2.5x10(3) at 9V MW are shown for first time in metal NC memory devices using the proposed distributed cycling scheme.
Genre Proceedings Paper
Topic Nonvolatile
Identifier 2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM,981-987