Record Details

Design and Analysis of High-Performance and Low-Power Quaternary Latch, Quaternary D Flip-Flop and XY Flip-Flop

NOPR - NISCAIR Online Periodicals Repository

View Archive Info
 
 
Field Value
 
Title Design and Analysis of High-Performance and Low-Power Quaternary Latch, Quaternary D Flip-Flop and XY Flip-Flop
 
Creator Shadwani, Mayank
Bansal, Urvashi
 
Subject Binary logic
Multi-valued logic
CMOS
Quaternary logic
Sequential circuitsr
Shift registe
 
Description 1004-1015
Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circuit designs. For
example, serious difficulties with limitations on the number of connections between an integrated circuit and the outside world
(pinout concern) and also the number of links within the circuit encountered in some VLSI circuit synthesis could be greatly
reduced if signals in the circuit could assume four or more states instead of only two. This research work shows a quaternary
logic-based latch, a level-sensitive flop, and an edge-sensitive flop. In most of the cases it is seen that a sequential digital circuit
produces two outputs which are complementary to each other. But in most of the designs, there is no need of having both the
outputs of the flip-flops, so one of the quaternary outputs can be removed from the circuit, resulting in a decrease in area and
static power. In quaternary circuits, several power sources or a single power supply source are employed. Those that have
several sources of supply use less energy. In multiple-valued logic we need the design to have multiple logic levels, like in
quaternary logic, GND is used for logic ‘0’, 1/3Vdd is used for logic ‘1’, 2/3Vdd is for logic ‘2’, and Vdd is for logic ‘3’. The
multi-Vdd design method is incompatible with the purpose of reducing the inter-chip and intra-chip connections. In order to
resolve this, a capacitive divider network is used while designing. The QFF is demonstrated with the necessary simulation
results using LTSpice tool and the simulations are performed using 32nm technology file. Finally, a quaternary shift register is
built to demonstrate the applicability and appropriate operation of the proposed QFF in larger sequential circuits.
 
Date 2022-12-16T09:33:35Z
2022-12-16T09:33:35Z
2022-12
 
Type Article
 
Identifier 0975-0959 (Online); 0301-1208 (Print)
http://nopr.niscpr.res.in/handle/123456789/61029
https://doi.org/10.56042/ijpap.v60i12.62642
 
Language en
 
Publisher NIScPR-CSIR, India
 
Source IJPAP Vol.60(12) [Dec 2022]