Record Details

Performance Comparison of Junctionless FinFET with Nanosheet FET and Device Design Guidelines

NOPR - NISCAIR Online Periodicals Repository

View Archive Info
 
 
Field Value
 
Title Performance Comparison of Junctionless FinFET with Nanosheet FET and Device Design Guidelines
 
Creator Saini, Sonia
Saini, Gaurav
 
Subject FinFET
Gate all around (GAA)
Junctionless
Nanosheet
Short channel effects (SCE)
 
Description 490-502
In this paper, the junctionless Fin Field Effect Transistor (FinFET) and nanosheet Field Effect Transistor (NSFET) with a
gate length of 12 nm are implemented using the Sentaurus Technology Computer-Aided Design (TCAD) tool. To compare
the junctionless FinFET and NSFET, simulations are done at constant threshold voltage. The NSFET outperformed FinFET
in terms of current driving capabilities, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), and intrinsic
voltage gain (AV). Further, the device design guidelines are presented for FinFET and NSFET in terms of geometrical
parameters. The simulation indicates that downscaling the gate length from 16 to 8 nm leads to an increase in SS and DIBL
by 21 and 68.49 % in FinFET whereas 19 and 70.14 % in nanosheet FET. The height variation of FinFET seems to make the
least impact on short channel effects (SCEs) while scaling the thickness of NSFET from 9 to 5 nm improves the DIBL and
SS by 61.9 % and 15.54 % respectively. In the case of scaling the width of FinFET from 10 to 5 nm, DIBL and SS increase
by 55.4 % and 14 % whereas scaling of nanosheet width from 24 to 12 nm gives 19.44 % and 1.37 % improvement in DIBL
and SS, respectively.
 
Date 2024-06-07T09:47:42Z
2024-06-07T09:47:42Z
2024-06
 
Type Article
 
Identifier 0975-0959 (Online); 0301-1208 (Print)
http://nopr.niscpr.res.in/handle/123456789/64050
https://doi.org/10.56042/ijpap.v62i6.7238
 
Language en
 
Publisher NIScPR-CSIR, India
 
Source IJPAP Vol.62(06) [June 2024]